The present invention relates to an information processing apparatus having a contention control function for a SoC (System on Chip) system bus.
FIG. 22 is a block diagram for schematically showing the architecture of a conventional information processing apparatus and FIG. 23 is a timing chart for explaining its operation.
As shown in FIG. 22, the conventional information processing apparatus has a system bus for connecting a plurality of transfer originator bus control units 1 through 3 (transfer originators A, B and C) for respectively sending transfer information and a plurality of transfer destination bus control units 4 and 5 (transfer destinations 1 and 2) for respectively receiving the transfer information to one another, and includes circuits (command buffers) 9 through 11 for storing precedent transfer information of the transfer originator bus control units 1 through 3; buses 6 through 8 for respectively connecting the transfer originator bus control units 1 through 3 to the command buffers 9 through 11; circuits (command arbiters) 13 and 14 for controlling contention of the transfer information between the transfer destination bus control units 4 and 5; a hierarchical bus 12 for connecting the command buffers 9 through 11 to the command arbiters 13 and 14; buses 21 and 22 for respectively connecting the command arbiters 13 and 14 to the transfer destination bus control units 4 and 5; circuits (read information arbiters) 50 through 52 for controlling the contention of read information; buses 37 through 39 for respectively connecting the read information arbiters 50 through 52 to the transfer originator bus control units 1 through 3; a hierarchical bus 40 for connecting the transfer destination bus control units 4 and 5 to the read information arbiters 50 through 52; circuits (decoders) 44 and 45 for identifying read information; and buses 48 and 49 for respectively connecting the decoders 44 and 45 to the transfer destination bus control units 4 and 5.
The operation of the information processing apparatus having the aforementioned architecture will now be described with reference to FIG. 23.
In FIG. 23, the ordinate indicates the states of the transfer originators and the transfer destinations, a transfer originator slot corresponds to a three-stage buffer for storing precedent transfer information, and a transfer destination slot corresponds to a three-stage buffer for storing read data notice information. The abscissa indicates time, and each time duration among times T1, T2, T3, T4, T5, T6 and T7 corresponds to an information processing unit time. Also, the priority for the command arbiters 13 and 14 and the read information arbiters 50 through 52 is in the order of the transfer originator A, the transfer originator B and the transfer originator C.
At the time T1, the transfer originator A issues two transfer information items to the transfer destination 1, the transfer originator B issues two transfer information items to the transfer destination 1 and the transfer originator C issues two transfer information items to the transfer destination 1 and one transfer information item to the transfer destination 2.
In a period between the times T1 and T2, since the transfer originator A has the highest priority according to the priority for the command arbiters 13 and 14, the transfer information items are transferred in the order of the transfer originator A, the transfer originator B and the transfer originator C. Also, the transfer destination 1 issues read information notices to the respective transfer originators.
At the time T2, the transfer originator A issues one transfer information item to the transfer destination 1, the transfer originator B issues one transfer information item to the transfer destination 1, and the transfer originator C issues one transfer information item to the transfer destination 1 and one transfer information item to the transfer destination 2.
In a period between the times T2 and T3, since the transfer originator A has the highest priority in accordance with the priority for the command arbiters 13 and 14, the transfer information items are transferred in the order of the transfer originator A, the transfer originator B and the transfer originator C. Also, the transfer destination 1 issues a read information notice to the transfer originator C.
At the time T3, the transfer originator C alone issues one transfer information item to the transfer destination 2. Also, the transfer destination 1 simultaneously issues a read information notice.
In a period between the times T4 and T6, read information notices issued by the respective transfer destinations are sent to the respective transfer originators in accordance with the priority for the read information arbiters 50 through 52.
In a conventional technique, a bus for supporting split transfer is employed in a bus system in which a plurality of modules are hierarchically connected through buses, but the contention control is performed independently in every bus of the transfer destinations as described above (see Japanese Laid-Open Patent Publication No. 2002-278923).